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            DFT Compiler培训班
   入.学.要.求

        学员学习本课程应具备下列基础知识:
        ◆ 有数字电路设计和硬件描述语言的基础或自学过相关课程。

   班.级.规.模.及.环.境
       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦
最近开课时间(周末班/连续班/晚班)
DFT Compiler培训班:2024年1月8日(请抓紧报名)
   实验设备
     ☆资深工程师授课

        
        ☆注重质量
        ☆边讲边练

        ☆合格学员免费推荐工作


        专注高端培训17年,曙海提供的课程得到本行业的广泛认可,学员的能力
        得到大家的认同,受到用人单位的广泛赞誉。

        ★实验设备请点击这儿查看★
   .最.新.优.惠.
       ◆在读学生凭学生证,可优惠500元。
   .质.量.保.障.

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、培训结束后免费提供半年的技术支持,充分保证培训后出效果;
        3、培训合格学员可享受免费推荐就业机会。

              DFT Compiler培训班

 

Overview
In this workshop, you will learn to use DFT Compiler to perform RTL and gate-level DFT checks and insert scan using top-down and bottom-up flows. The workshop will show you how to analyze the reported data to identify common DFT violations and then fix the original RTL design. The class explores essential techniques to support large, multi-million gate SOC designs including the bottom-up scan insertion flow in the logical (Design Compiler) domain. Techniques learned include: performing scan insertion in a top-down flow; meeting scan requirements for number of scan chains, maximum chain length, and reusing functional pins for scan testing; and using Adaptive Scan (DFTMAX) to insert additional DFT hardware to reduce the test time and the test data volume required for a given fault coverage. ObjectivesAt the end of this workshop the student should be able to:
  • Define the test protocol for a design and customize the initialization sequence, if needed
  • Perform DFT checks at both the RTL and gate levels
  • State common design constructs that cause typical DFT violations
  • Automatically correct certain DFT violations at the gate level using AutoFix
  • Insert scan to achieve well-balanced top-level scan chains and other scan design requirements
  • Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and place & route.
  • Implement Rapid Scan Synthesis (RSS) in a top-down scan insertion flow achieving well-balanced scan chains
  • Modify a bottom-up scan insertion script for full gate-level designs to use test models/ILMs with RSS and run it
  • Preview top-level chain balance using test models/ILMs after block-level scan insertion and revise block-level scan architecture as needed to improve top-level scan chain balance.
  • Modify a scan insertion script to include DFT-MAX Adaptive Scan compression
Audience Profile
Design and Test engineers who need to identify and fix DFT violations in their RTL or gate-level designs, insert scan into multi-million-gate SoCs, and export design files to ATPG and P&R tools Prerequisites
There are no prerequisites for this workshop. Prior experience with Design Compiler, Design Vision, and with writing Synopsys Tcl scripts is useful, but not required. Course 1.
  • Introduction to Scan Testing
  • DFT Compiler Flows
  • DFT Compiler Setup
  • Test Protocol
  • DFT Design Rule Checks
2.
  • DFT DRC GUI Debug
  • DRC Fixing
  • Top-Down Scan Insertion
3.
  • Exporting Files
  • High Capacity DFT Flows
  • Multi-Mode DFT
  • DFT MAX
Synopsys Tools Used
  • DFT Compiler 2010.03-SP3
  • Design Vision 2010.03-SP3
  • Design Compiler 2010.03-SP3
  • TetraMAX 2010.03-SP3