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 IC Compiler 1 培训

   课程背景
The class begins with how to load the required synthesis and physical data required by IC Compiler (data setup), followed by creating a floorplan, including power grid, to meet timing and routeability throughout the flow (design planning). The placement flow focuses on optimizing the placement and logic for timing, congestion, power, and scan-chain ordering. The CTS unit covers controlling and building clock trees and performing additional timing optimization, followed by routing of the clock nets. In the routing unit, you will learn the signal routing and optimization steps based on the Zroute mode, including concurrent via doubling and antenna fixing. The chip finishing unit includes steps to improve yield and reliability, including wire spreading/widening, diode insertion, inserting filler cells, redundant via insertion, and metal filling.
Every lecture is accompanied by a comprehensive hands-on lab.
   课.程.目.标
  • Perform data setup, which includes loading required synthesis and physical data, creating a Milkyway design library, and applying common timing and optimization controls
  • Create a non-hierarchical chip-level floorplan that will be routable and will achieve timing closure
  • Perform placement and related optimizations to minimize timing violations, congestion, and power
  • Analyze congestion maps and timing reports
  • Perform pre-CTS power optimization
  • Perform clock tree synthesis
  • Analyze clock and timing results post-CTS
  • Route the clock nets
  • Execute a Zroute-based signal routing flow, with concurrent via doubling and antenna fixing
  • Analyze and fix physical DRC and LVS violations
  • Perform functional ECOs
  • Perform chip finishing steps
  • Generate output files required for final validation/verification
   班.级.规.模.及.环.境
       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。注意:本课程一旦开课不予退费。
   时间地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦
最近开课时间(周末班/连续班/晚班):
IC Compiler 1班:2024年1月8日(请抓紧报名)
   学时和费用
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   .最.新.优.惠.
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   .质.量.保.障.

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、培训结束后免费提供半年的技术支持,充分保证培训后出效果;
        3、培训合格学员可享受免费推荐就业机会。

   .课.程.大.纲.:

IC Compiler 1 培训

课程内容:

阶段 1
  • Introduction and Overview
  • Data Setup and Basic Flow
  • Design Planning
阶段 2
  • Design Planning (Lab continued)
  • Placement
  • Clock Tree Synthesis
阶段 3
  • Clock Tree Synthesis (Lab continued)
  • Routing
  • Chip Finishing
  • Customer Support